1. Field of the Invention
The invention relates to a nitrogen-doped silicon wafer and to a process for producing the silicon wafer by means of a heat treatment.
2. Background Art
Silicon single crystals, which are generally produced using the Czochralski crucible pulling (CZ) process or the crucible-free float zone process (FZ) have a number of impurities and defects. The single crystals are cut into wafers, subjected to a multiplicity of machining steps in order to obtain the desired surface quality, and finally are generally used for the fabrication of electronic components. If special precautions are not taken, the abovementioned defects are also present at the surface of the wafers, where they can have an adverse effect on the function of the electronic components produced thereon.
One significant type of defect is what are known as COPs (crystal originated particles), accumulations of vacancies forming small voids with a size of typically from 50 to 150 nm. According to the Voronkov theory, they occur whenever the ratio of the pulling rate and thermal gradient, measured over the interface between silicon melt and silicon ingot, exceeds a critical value. This is described as a pulled “vacancy-rich” ingot. The size of the COPs is significantly smaller at the edge of a silicon wafer than in the center, since the ingot shell cools more quickly than the ingot center, and therefore the time during which COPs can grow through vacancy agglomeration is shorter.
These defects can be measured with the aid of numerous methods. Partial etching of the defects by means of an SC1 solution (NH3/H2O2/H2O) at approximately 85° C. for 20 minutes followed by scattered light measurement is one way of checking for COPs on the wafer surface. Partial etching of the defects by means of a Secco etch for 30 minutes with silicon removal of approximately 30 μm and subsequent counting also allows these defects to be determined. If the defects which have what is known as a flag are counted, this is known as FPD (flow pattern defects). The result obtained is an FPD density per unit area which, taking into account the amount of material removed during the preparatory etch, can be converted into a density per unit volume. The same defects can also be measured by means of IR-LST (“infrared light scattering tomography”), in which an Nd-YAG laser beam is scattered at the defects in the silicon wafer, and the scattered light is detected at an angle of 90° to the laser beam. According to this measurement method, the defects are referred to as LSTD defects. A commercially available measuring unit which operates on the basis of this principle is marketed, for example, by Mitsui, Japan (appliance designation MO6) and is able to detect COPs down to a depth of 6 μm and to a minimum diameter of 35 nm.
In the text which follows, all these defects, which have for historic reasons been described differently but are caused by the same physical principle of agglomeration of vacancies, are referred to as COPs.
The prior art has disclosed processes for the heat treatment of silicon wafers which considerably reduce the COP density in a layer near to the surface and lead to what is known as a “COP-free zone” at the surface.
It is also known from the prior art to dope a silicon single crystal with nitrogen while it is being produced by means of the Czochralski crucible pulling process. According to EP 829 559 A1, the doping with nitrogen shifts the defect size distribution toward smaller defects. It is known from EP 1 087 042 A1 that doping with nitrogen leads to the formation of elongate or plateletlike COPs rather than octahedral COPs during the crystal pulling.
It is also known from the abovementioned documents for the nitrogen-doped silicon wafer to be subjected to a heat treatment at a temperature of over 1000° C. under a nonoxidizing atmosphere, for example hydrogen or argon or a mixture thereof, in order to remove COPs from a layer at the surface of the wafer. The layer at the surface, in which the COP density is reduced to less than half the value prior to the heat treatment, is at least 0.5 μm thick according to EP 1 087 042 A1.
It is also known that nitrogen doping promotes the formation of oxygen precipitates (“bulk micro defects”=BMDs), since the nitrogen boosts the nucleation for this type of defect. A sufficiently high BMD density of typically 5·108 to 2·1010 cm−3, preferably over the entire wafer thickness, but at least in the vicinity of the zone which is active for semiconductor devices, is necessary in order to allow what is known as the gettering of metal atoms in the interior of the silicon wafer. Only in this way is it possible to keep the layer close to the surface, in which components are subsequently to be fabricated, free of undesirable metal impurities.
Another advantage of the nitrogen doping is the greater hardness of the silicon wafer which can be achieved as a result, so that the formation of slippages can be effectively avoided during the heat treatment. This desirable effect, which is exploited in the prior art (T. Müller et al. in: Semiconductor Silicon 2002 (9th International Symposium), H. R. Huff, L. Fabry and S. Kishino (Eds.), The Electrochemical Society Proceedings Vol. 2002-2, 194-201) occurs in particular above a nitrogen concentration of 8·1014 atoms/cm3. The nitrogen doping leads to an increase in the upper yield stress (τUY). This material parameter indicates the Minimum shear stress which needs to be applied in order for a solid to be deformed not just elastically reversibly but plastically irreversibly. If the upper yield stress is increased by doping with nitrogen, plastic deformation of the silicon wafer, i.e. the formation of slippages, only occurs with the application of higher shear stresses. It was possible to demonstrate this effect both for FZ silicon pulled without a crucible and for CZ silicon (H. D. Chiou et al., VLSI Sci. And Tech., ECS, Pennington, 59, 1984).
The heat treatment of silicon wafers to dissolve COPs close to the surface generally takes place at temperatures between 1100° C. and 1300° C. for a period of from 30 minutes to three hours. A vertical furnace, in which a multiplicity of silicon wafers are treated simultaneously, arranged parallel above one another at a defined pitch, is generally used for this purpose. The silicon wafers are mounted in a holding device, known as the “boat”, with each silicon wafer resting individually on a support, the substrate holder. Boats of this type are described for example in GB 2273551, U.S. Pat. No. 6,065,615 or U.S. Pat. No. 6,133,121. Substrate holders are described, for example, in US 2004/0040632A1 or WO 2004/090967A1. During the heat treatment, the boat is located in a generally cylindrical process chamber, which is heated from the lateral surface.
As a result of the heating from the lateral surface of the process chamber, a temperature difference between the edge and center of each silicon wafer is formed during the heating and cooling. The associated different thermal expansion during heating or contraction during cooling gives rise to thermal stresses. Moreover, the weight of the silicon wafer itself, in conjunction with the substrate holder, leads to gravity-induced stresses. If the sum of the two stress components exceeds the upper yield stress of the silicon wafer, undesirable slippages occur, reducing the yield in the fabrication of electronic components, since, for example, metal impurities preferentially accumulate at these crystal defects.
The larger the diameter of the silicon wafers, the greater the weight per unit area, and therefore the gravity-induced stresses, become. This drawback is not compensated for by a corresponding increase in the wafer thickness. The greater distance between the heated lateral surface of the process chamber and the center of the wafer with a larger wafer diameter also leads to higher thermal stresses. For this reason, the risk of the formation of slippages in silicon wafers with a diameter of 300 mm or more increases considerably compared to the silicon wafers which have hitherto been customary, with a diameter of at most 200 mm. Therefore, simple adaptation of the concepts for suppressing the formation of slippages with smaller wafer diameters is likewise not possible.
Therefore, doping with nitrogen is a standard process in the production of silicon wafers with a diameter of 200 mm or more in order to avoid slippage in the wafers at high process temperatures. This effect is of considerable technical importance in particular for the heat treatment of silicon wafers with a diameter of 300 mm which is used to dissolve COPs close to the surface, since a significantly higher yield can be achieved in this way.
As has been indicated above, doping with nitrogen is advantageous for a number of reasons. However, it has emerged that the heat treatment of a silicon wafer doped with nitrogen leads to additional defects on its surface. Since future component generations will require patterning in the nanometer range, these defects lead to device errors, such as for example lithography defects or a deterioration in what is known as the GOI (gate oxide integrity) value of the transistor gate oxide. Therefore, the occurrence of these defects needs to be avoided as far as possible.
On the other hand, for the reasons mentioned above, it is in many cases not possible to do without doping with nitrogen. Therefore, all the heat-treated silicon wafers with a diameter of 300 mm which are known in the prior art lead to a relatively low yield of functioning electronic components if they are produced using the most advanced component technologies. This problem is solved by the invention.